00852nam 22002413 4500 37335 0-89838-302-1 37335 20130903d u||y0frey50 ba eng US ||||||||||||| Switch-Level timing simulation of MOS VLSI circuits Vasant B. Rao, David V. Overhauser, Timothy N.Trick Boston Kluwer Academic Publishers 1989 x, 210 p. The Kluwer international series in engineering and computer science References : P.193 - 204 Index : P. 205 - 208 33362 Circuite integrate Integrarea scară foarte mare Simularea pe calculator 621.38.049.774.2=111 33359 Rao Vasant B. 33360 Overhauser David V. 33361 Trick Timothy N. BK 13 0 0 0 2013-10-22 325959 SC SC SA SC13100714 42.00 MN SC83851 621 S98 2020-09-01 0 BK 42.00 2017-11-08